Title :
High speed bit-serial parallel processing on array architecture
Author :
Ito, Kazuhito ; Shimizugashira, Takenobu ; Kunieda, Hiroaki
Author_Institution :
Dept. of Electr. & Electr. Syst., Saitama Univ., Urawa, Japan
Abstract :
Word-parallel bit-serial processing is a solution to high speed processing suitable for VLSI. In this paper a new bit-serial parallel processing architecture is proposed. A VLSI chip for a digital filter is designed based on the proposed architecture and it is implemented on a gate array chip. Through the implementation, it is verified that bit-serial parallel processing on an array architecture achieves high speed processing and easy design
Keywords :
CMOS logic circuits; VLSI; digital filters; integrated circuit design; logic arrays; low-pass filters; systolic arrays; 0.5 mum; 50 MHz; 520 kHz; VLSI chip; array architecture; digital filter; gate array chip; high speed bit-serial parallel processing; two metal layered sea-of-gates CMOS gate array chip; Clocks; Data communication; Digital filters; Filtering theory; Parallel processing; Process design; Registers; Signal processing algorithms; Systolic arrays; Very large scale integration;
Conference_Titel :
Design Automation Conference, 1997. Proceedings of the ASP-DAC '97 Asia and South Pacific
Conference_Location :
Chiba
Print_ISBN :
0-7803-3662-3
DOI :
10.1109/ASPDAC.1997.600355
