CQ switch performance analysis from the point of buffer size and scheduling algorithms

In this paper, we present the performance analysis of the 32×32 crosspoint queued (CQ) switch. The CQ switch architecture has been recently brought back into focus since modern technology enables an easy implementation of large buffers in crosspoints. An advantage of this solution is the absence of credit based control communication between linecards and schedulers. In this paper, the performances of four algorithms (longest queue first, round robin, exhaustive round robin and frame based round robin matching), are analyzed and compared. The results obtained for the CQ switch are compared with the output queued switch. Throughput, average cell latency and instantaneous packet delay variance are evaluated under uniform and nonuniform traffic patterns. Also, original iterative method for CQ switch throughput calculation under the uniform traffic is presented. The results will show that the longest queue first algorithm has the highest throughput in many simulated cases, but the highest average cell latency and delay variance among observed algorithms. It will also be shown that the choice of the scheduling algorithm does not play a role in the switch performance if the buffers are long enough. This will prove that some form of round robin based algorithms become a better choice for implementation due to their simplicity, small hardware requirements and avoidance of the starvation problem, which is a major drawback of the longest queue first algorithm. The proposed iterative method for throughput calculation gives results very close to the results obtained by numerous simulations, especially for larger switch and long buffers.