LART: flexible, low-power building blocks for wearable computers

Author

Bakker, Jan-Derk ; Langendoen, Koen ; Sips, Henk

Author_Institution

Fac. of Inf. Technol. & Syst., Delft Univ. of Technol., Netherlands

fYear

2001

fDate

36982

Firstpage

255

Lastpage

259

Abstract

To ease the implementation of different wearable computers, we developed a low-power processor board (named LART) with a rich set of interfaces. The LART supports dynamic voltage scaling, so performance (and power consumption) can be scaled to match demands: 59-221 MHz, 106-640 mW. High-end wearables can be configured from multiple LARTs operating in parallel; alternatively, FPGA boards can be used for dedicated data-processing, which reduces power consumption significantly

Keywords

field programmable gate arrays; microprocessor chips; performance evaluation; portable computers; reconfigurable architectures; FPGA; LART; dedicated data-processing; dynamic voltage scaling; low-power processor board; performance; power consumption; wearable computers; Application software; Augmented reality; Biomedical monitoring; Central Processing Unit; Energy consumption; Field programmable gate arrays; Hardware; Linux; Wearable computers; Wearable sensors;

fLanguage

English

Publisher

ieee

Conference_Titel

Distributed Computing Systems Workshop, 2001 International Conference on

Conference_Location

Mesa, AZ

Print_ISBN

0-7695-1080-9

Type

conf

DOI

10.1109/CDCS.2001.918714

Filename

918714

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3060625