An LSI implementation of the simple serial synchronized multistage interconnection network

A high speed switch is a critical component of multiprocessors. Multistage interconnection network (MIN) has been utilized as a switch for connection processors and memory modules in multiprocessors. Unlike the crossbar, it consists of small switching elements, and provides a high bandwidth with relatively small hardware. Most of traditional MINs are blocking networks and packets are transferred in the store-and-forward manner between switching elements with bit-parallel (8-64bits) lines. Since the width of communication paths and transferred manner cause pin-limitation problems and complicated structure, the high density implementation and high speed clock is not utilized. In order to solve these problems, we implemented the SSS-PBSF chip. This switch uses the PBSF connection structure which can obtain a higher bandwidth than that of crossbar with connecting banyan networks in a 3D direction. A simple serial synchronized (SSS) style control mechanism is adopted both for high speed operation and solving the pin-limitation problem