DocumentCode :
3061084
Title :
A VLSI chip for computing the medial axis transform of an image
Author :
Ranganathan, N. ; Doreswamy, K.B.
Author_Institution :
Dept. of Comput. Sci. & Eng., Univ. of South Florida, Tampa, FL, USA
fYear :
1995
fDate :
18-20 Sep 1995
Firstpage :
36
Lastpage :
43
Abstract :
We describe a new special purpose VLSI architecture for computing the medial axis transform of an image. The architecture is systolic and is based on an algorithm that achieves a high degree of parallelism. The proposed algorithm computes the skeleton of multiple objects in an image in linear time by making 2 scans over the 4 distance transform of the image. The algorithm is mapped onto a linear systolic array of simple processing elements (PEs) and for an N×N image, the architecture requires N PE´s. The entire array can be realized in a single VLSI chip. The proposed hardware can perform thinning on a 512×512 image in 2.59 msec and on a 256×256 image in 0.327 msec. A prototype CMOS VLSI chip implementing the proposed architecture has been designed and verified
Keywords :
VLSI; image processing; image processing equipment; microprocessor chips; parallel algorithms; systolic arrays; transforms; VLSI chip; image transform; input image data; linear systolic array; medial axis transform; parallel algorithm; prototype CMOS chip; simple processing elements; special purpose VLSI architecture; systolic architecture; Character recognition; Computer science; Film bulk acoustic resonators; Microelectronics; Optical character recognition software; Pixel; Skeleton; Terminology; Text analysis; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer Architectures for Machine Perception, 1995. Proceedings. CAMP '95
Conference_Location :
Como
Print_ISBN :
0-8186-7134-3
Type :
conf
DOI :
10.1109/CAMP.1995.521017
Filename :
521017
Link To Document :
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