Title :
A scalable architecture for discrete wavelet transform
Author :
Syed, Shafiullah B. ; Bayoumi, Magdy A.
Author_Institution :
Center for Adv. Comput. Studies, Southwestern Louisiana Univ., Lafayette, LA, USA
Abstract :
We present the design and prototyping of an efficient systolic architecture which performs both forward and inverse discrete wavelet transform. The proposed architecture consists of a linear array of processing elements, each of which has an adder and a multiplier and fixed number of I/O channels. The wavelet transform is computed by convolution and by mapping the computation on to a linear array of systolic processing elements. The design of the architecture has been shown to be simple, scalable and has the advantage of low I/O bandwidth. The number of processing elements is independent of the size of the input. The architecture has been prototyped using 2μm p-well CMOS technology and has been developed in the CADENCE Edge Design Framework environment
Keywords :
CMOS digital integrated circuits; convolution; signal processing equipment; systolic arrays; wavelet transforms; CADENCE Edge Design Framework environment; CMOS technology; I/O channels; adder; convolution; forward discrete wavelet transform; inverse discrete wavelet transform; linear array; low I/O bandwidth; multiplier; scalable architecture; systolic architecture; systolic processing elements; Bandwidth; CMOS technology; Computer architecture; Continuous wavelet transforms; Convolution; Discrete wavelet transforms; Finite impulse response filter; Prototypes; Signal processing; Signal resolution;
Conference_Titel :
Computer Architectures for Machine Perception, 1995. Proceedings. CAMP '95
Conference_Location :
Como
Print_ISBN :
0-8186-7134-3
DOI :
10.1109/CAMP.1995.521018
