Title :
2D compact modeling of the threshold voltage in triple- and Pi-gate transistors
Author :
Ritzenthaler, R. ; Lime, F. ; Faynot, O. ; Cristoloveanu, S. ; Iñiguez, B.
Author_Institution :
Dept. of Electron. Eng., Rovira i Virgili Univ., Tarragona, Spain
Abstract :
Multiple-gate transistors are considered as very promising candidates for the 22 nm technological node. They are named Triple-gate FETs (TGFETs) when the gate controls three sides of the silicon body; if the channel etch process step penetrates in the Buried Oxide (BOX), the transistor is named Pi-gate FET. There is currently a strong need for compact models of such architectures, in order to evaluate their circuit performance. In this work, the threshold voltage modeling of long channels TGFET and Pi-gate FET is studied.
Keywords :
etching; field effect transistors; semiconductor device models; 2D compact modeling; Pi-gate FET; Pi-gate transistors; TGFET; buried oxide; channel etch process; multiple-gate transistors; threshold voltage modeling; triple-gate FETs; triple-gate transistors; Educational institutions; Etching; FETs; Laboratories; Laplace equations; MOSFETs; Semiconductor device modeling; Silicon; Solid modeling; Threshold voltage;
Conference_Titel :
Semiconductor Device Research Symposium, 2009. ISDRS '09. International
Conference_Location :
College Park, MD
Print_ISBN :
978-1-4244-6030-4
Electronic_ISBN :
978-1-4244-6031-1
DOI :
10.1109/ISDRS.2009.5378333