Systolic cellular logic: architecture and performance evaluation

Author

Rogers, Richard P. ; MacDuff, Ian G. ; Tanimoto, Steven L.

Author_Institution

Dept. of Comput. Sci. & Eng., Washington Univ., Seattle, WA, USA

fYear

1995

fDate

18-20 Sep 1995

Firstpage

51

Lastpage

58

Abstract

We describe a systolic cellular logic architecture implemented in the systolic cellular logic (SCL) VLSI chip. The SCL chip´s hardware support for virtual processing is intended to provide low cost, high performance image processing. We present empirical performance data for the Abingdon Cross benchmark which indicate that the SCL chip successfully delivers high performance at a relatively low cost. We further substantiate the SCL´s success with empirical performance data for a complete experimental shape extraction protocol based on mathematical morphology

Keywords

VLSI; cellular logic; image processing; image processing equipment; performance evaluation; systolic arrays; Abingdon Cross benchmark; SCL VLSI chip; empirical performance data; experimental shape extraction protocol; hardware support; high performance image processing; mathematical morphology; performance evaluation; systolic cellular logic VLSI chip; systolic cellular logic architecture; virtual processing; Costs; Hardware; Image processing; Logic design; Logic programming; Morphology; Pixel; Protocols; Shape; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Architectures for Machine Perception, 1995. Proceedings. CAMP '95

Conference_Location

Como

Print_ISBN

0-8186-7134-3

Type

conf

DOI

10.1109/CAMP.1995.521019

Filename

521019