The RDT network router chip

The RDT network router chip is a versatile router for the massively parallel computer prototype JUMP-1. The major goal of this project is to establish techniques for building an efficient distributed shared memory on a massively parallel processor. For this purpose, the reduced hierarchical bit-map directory (RHBD) schemes are used for efficient cache management of the distributed shared memory. In order to implement (RHBD) schemes efficiently, we proposed a novel interconnection network RDT (recursive diagonal torus), and developed a sophisticated router chip for the RDT which equips a hierarchical multicast mechanism without deadlock and acknowledge combining mechanism. By using the 0.5μBiCMOS SOG technology it can transfer all packets synchronized with a unique CPU clock(60MHz). Long coaxial cables are directly driven with the ECL interface of this chip. The mixed design approach with schematic and VHDL permits the development of the complicated chip with 90,522 gates in a year