Execution time measurement of a vector operation on LSC-Based DSP

In this paper, we describe the performance measurement of a new DSP processor based on the dataflow execution model. Our proposed DSP processor is in contrast to most recent DSP processors based on von Neumann paradigm. We call our DSP as LSC-based DSP because it is a specialized Loop Structured Computer (LSC) which is a parallel dataflow computer developed in our laboratory. In our measurement, we choose a vector operation as a benchmark algorithm because a vector operation is involved in most DSP algorithms and inherently equivalent to a program in a dataflow computer. LSC-based DSP is designed in hardware description language and implemented on a field programmable gate array (FPGA). We measure the execution time of a vector operation on LSC-based DSP with varying some design parameters. The measurement result shows the ability for parallel execution of LSC-based DSP with several dataflow processing elements. In practice, the execution time of LSC-based DSP with seven processing elements is approximately five times shorter than that with one processing element.