A tale of two architectures: TI TMS 320 SPC vs. DEC Micro/J-11

The nearly simultaneous introduction of DSP (TMS 320) and gp (the J-11 "PDP-11/70-on-a-chip") microcomputers, both with 20 MHz clock rates and 200 nsec add/subtract times allows us to compare similar implementations of different architectures for various DSP benchmarks. We also compare the 320 to a "future" J-11 in which the addition of a 16×16-bit, 200 nsec array multiplier makes the two micromachines "identical" in terms of apparent raw processing power. The conclusions are that although the TMS 320 is a cultural descendent of the PDP-11, the TI machine has at least two significant architectural innovations which account for its enhanced processing speed relative to the PDP-11. These attributes are the use of the barrel shifter in time-transparently scaling data and the need for programmer look-ahead in register-based data addressing. The benchmark programs used to examine the relative machine efficiencies include windowing, autocorrelation, complex-to-magnitude conversion, lattice speech synthesis, and the FFT.