Title :
A VLSI architecture for 2D object classification based on tree matching
Author :
Schaffer, Maureen ; Chen, Tom
Author_Institution :
Dept. of Electr. Eng., Colorado State Univ., Fort Collins, CO, USA
Abstract :
This paper presents a real-time classification algorithm for 2D object contours using a multi-resolution tree model which is implemented in a modular VLSI architecture. The hardware implementation takes advantage of pipelining, parallelism, and the speed of VLSI technology to perform real-time object classification. Using the multi-resolution tree model, the classification algorithm is invariant under 2D similarity transformations and recognizes the visible portions of occluded objects. The VLSI classification system is implemented in 0.8 μm CMOS and is capable of performing 34000 matchings per second
Keywords :
CMOS digital integrated circuits; VLSI; computer vision; digital signal processing chips; image classification; image matching; object recognition; pipeline processing; real-time systems; systolic arrays; 0.8 mum; 2D object classification; 2D similarity transformations; VLSI architecture; VLSI classification system; classification algorithm; multi-resolution tree model; parallelism; pipelining; real-time classification algorithm; tree matching; Biological system modeling; CMOS technology; Classification tree analysis; Clocks; Computer applications; Hardware; Parallel processing; Pipeline processing; Silicon; Very large scale integration;
Conference_Titel :
Computer Architectures for Machine Perception, 1995. Proceedings. CAMP '95
Conference_Location :
Como
Print_ISBN :
0-8186-7134-3
DOI :
10.1109/CAMP.1995.521030
