A 64 parallel integrated memory array processor and a 30 GIPS real-time vision system

Author

Fujita, Yoshihiro ; Yamashita, Nobuyuki ; Okazaki, Shin´chiro

Author_Institution

NEC Corp., Kawasaki, Japan

fYear

1995

fDate

18-20 Sep 1995

Firstpage

242

Lastpage

249

Abstract

Describes a parallel-processor LSI chip (the Integrated Memory Array Processor, IMAP) and a compact real-time vision system (RVS-2). The IMAP integrates 64 8-bit processors, which operate in a SIMD manner, and 2-Mbit image memory on a single chip, and has peak performance of 3.84 GIPS. The RVS-2 consists of 8 IMAPs, a video interface, a control LSI chip (the Real-time Vision System Controller, RVSC) and a host workstation. RVSC is a 16-bit processor which carries out global data operations as well as providing an instruction stream to IMAP processors. In the RVS-2 system, the IMAP processors accomplish data-parallel operations, the RVSC applies global data operations to the results, and the host workstation carries out higher-level recognition tasks using the results obtained by the IMAPs and the RVSC. The peak performance of the RVS-2 is 30 GIPS and most of the basic image processing is carried out in 0.1 to 0.7 ms, which is 50 to 300 times faster the video rate

Keywords

computer vision; digital signal processing chips; image processing equipment; image recognition; integrated memory circuits; large scale integration; parallel machines; real-time systems; 0.1 to 0.7 ms; 16 bit; 2 Mbit; 3.84 GIPS; 30 GIPS; 8 bit; IMAP; RVS-2; RVSC; SIMD processors; control LSI chip; data-parallel operations; global data operations; high-level recognition tasks; host workstation; image memory; image processing; instruction stream; parallel integrated memory array processor; parallel-processor LSI chip; peak performance; real-time vision system; video interface; video rate; Clocks; Data processing; Image processing; Large scale integration; Machine vision; National electric code; Prototypes; Random access memory; Real time systems; Shift registers;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Architectures for Machine Perception, 1995. Proceedings. CAMP '95

Conference_Location

Como

Print_ISBN

0-8186-7134-3

Type

conf

DOI

10.1109/CAMP.1995.521046

Filename

521046