DocumentCode :
3061854
Title :
A fast asynchronous algorithm for linear feature extraction on IBM SP-2
Author :
Chung, Yongwha ; Prasanna, Viktor K. ; Wang, Cho-Li
Author_Institution :
Dept. of Electr. Eng. Syst., Univ. of Southern California, Los Angeles, CA, USA
fYear :
1995
fDate :
18-20 Sep 1995
Firstpage :
294
Lastpage :
301
Abstract :
We present a fast parallel implementation of linear feature extraction on IBM SP-2. We first analyze the machine features and the problem characteristics to understand the overheads in parallel solutions to the problem. Based on these, we propose an asynchronous algorithm which enhances processor utilization and overlaps communication with computation by maintaining algorithmic threads in each processing node. Our implementation shows that, given a 512×512 image, the linear feature extraction task can be performed in 0.065 seconds on a SP-2 having 64 processing nodes. A serial implementation takes 3.45 seconds on a single processing node of SP-2. A previous implementation on CM-5 takes 0.1 second on a partition of 512 processing nodes. Experimental results on various sizes of images using 4, 8, 16, 32, and 64 processing nodes are also reported
Keywords :
distributed memory systems; edge detection; feature extraction; message passing; parallel algorithms; CM-5; IBM SP-2; algorithmic threads; fast asynchronous algorithm; fast parallel implementation; linear feature extraction; linear feature extraction task; machine features; parallel solutions; problem characteristics; processing node; processing nodes; processor utilization; Computer architecture; Feature extraction; High performance computing; Image edge detection; Message passing; Multiprocessor interconnection networks; Phase detection; Protocols; Switches; Yarn;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer Architectures for Machine Perception, 1995. Proceedings. CAMP '95
Conference_Location :
Como
Print_ISBN :
0-8186-7134-3
Type :
conf
DOI :
10.1109/CAMP.1995.521053
Filename :
521053
Link To Document :
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