Realization of digital filter algorithms by use of a high speed parallel processing architecture

This paper presents a system, which generates code for a high speed parallel computer architecture taking as input the tolerance schemes of digital filters. The multi-processor system consists of data-, I/O-processors and a multiport memory. The interconnection network is a crossbar. The data-processors contain a private memory for the program instructions and local register blocks in which intermediate operands are stored. All system components operate synchronously.