Title :
A CMOS delayed locked loop (DLL) for reducing clock skew to under 500 ps
Author :
Kim, Yong-Bin ; Chen, Tom
Author_Institution :
Dept. of Electr. Eng., Colorado State Univ., Fort Collins, CO, USA
Abstract :
This paper presents a variable delay line DLL circuit implemented in a 0.8 μm CMOS technology. A phase detector and two charge pump circuits calibrate the delay per stage of the delay line using push-pull type clock synchronization scheme. The delay line can be programmed 6 to 18 stages. The DLL circuit is capable of reducing clock skew from 1-3 ns to below 500 ps for clock frequencies from 50 Mhz to 150 Mhz
Keywords :
CMOS integrated circuits; VLSI; circuit CAD; delay circuits; synchronisation; 0.8 micron; 50 to 150 MHz; CMOS delayed locked loop; charge pump circuits; clock skew; phase detector; push-pull type clock synchronization; variable delay line DLL circuit; CMOS technology; Charge pumps; Circuits; Clocks; Delay lines; Phase detection; Phase frequency detector; Phase locked loops; Silicon; Voltage;
Conference_Titel :
Design Automation Conference, 1997. Proceedings of the ASP-DAC '97 Asia and South Pacific
Conference_Location :
Chiba
Print_ISBN :
0-7803-3662-3
DOI :
10.1109/ASPDAC.1997.600362
