Techniques for a low-voltage low-power linear MOS transconductor

A bias-offset transconductor is known as a linear MOS transconductor. The transconductor requires some peripheral circuits, which are a floating voltage source and a biasing current source. This paper presents a design of a linear transconductor/multiplier for low-voltage and low-power operation with two techniques. One is a method to realize high-accuracy floating voltage source employing low-voltage cascode current mirrors. The other is use of the adaptively biasing circuit to reduce wasteful operating current without reduction of the operating range. Simulation results show that the proposed techniques are effective to realize low-voltage low-power transconductor.