V2X: An Automated Tool for Building SystemC-Based Simulation Environments in Designing Multicore Systems-on-Chips

Hardware/software (HW/SW) co-design has become an important issue for system design, and simulation environments have been utilized widely to shorten the development cycle. However, traditional hardware description languages (HDL), e.g., Verilog and VHDL, which are used by hardware designers to describe the hardware and model the hardware in a detailed simulated environment, are not appropriate for the purpose of HW/SW co-design. Instead, SystemC provides a higher-level simulation environment to the developers and is more suitable for HW/SW co-design. Furthermore, HDL-based simulation environments are far too slow to execute parallel programs as the number of processor cores increases. Thus, one would have liked an automated tool for converting existing HDL-based chip designs to SystemC or even higher-level functional descriptions so that the simulation speed would be acceptable for multicore systems. However, since existing tools failed to accomplish that, we developed an automated tool, called V2X, to convert Verilog chip designs to SystemC. In this paper, we show that complicated Verilog-based multicore chip descriptions were translated into SystemC descriptions automatically and resulted in better performance and programmability. In our case study, V2X successfully translated the 8-core OpenSPARC T1 system-on-chip into SystemC. Without further abstraction, the simulation speed was improved by ~40 times. The two-stage translation scheme makes V2X flexible and extensible, which paves the way for further abstraction to speed up the simulation environment.