Error-Correcting Codes for Concurrent Error Correction in Bit-Parallel Systolic and Scalable Multipliers for Shifted Dual Basis of GF(2^m)

This work presents a novel bit-parallel systolic multiplier for the shifted dual basis of GF(2^m). The shifted dual basis multiplication for all trinomials can be represented as the sum of two Hankel matrix-vector multiplications. The proposed multiplier architecture comprises one Hankel multiplier and one (2m-1)-bit adder. The algebraic encoding scheme based on linear cyclic codes is adopted to implement the multiplications with concurrent error correction (CEC). The latency overhead is analytically demonstrated to require extra four clock cycles than as compared by the multiplier without CEC. The block Hankel matrix-vector representation is used to derive a CEC scalable SDB multiplier. In the binary field GF(2⁸⁴), the space overhead of the proposed bit-parallel architecture using cyclic code is around 22.8%. The proposed CEC scalable multiplier given by seven or fewer injection errors can correct nearly 99.6% of error correction. Unlike the existing concurrent error detection multipliers that apply the parity prediction scheme, the proposed architectures have multiple error-detection capabilities.