Title :
VLSI interconnect process integration
Author :
Kikkawa, Takamaro
Author_Institution :
Res. Center for Nanodevices & Syst., Hiroshima Univ., Japan
Abstract :
This paper describes VLSI interconnect process integration with respect to ULSI scaling. Both resistivity and capacitance are key factors for materials used in the interconnect process integration. In order to reduce parasitic resistances of sub-quarter micron CMOS transistors, salicide technologies have been developed for gate and source/drain electrodes. Copper interconnects and low-k interlayer dielectrics, in conjunction with CMP planarization, have been developed to reduce RC delay for future scaled ULSIs
Keywords :
CMOS integrated circuits; ULSI; VLSI; capacitance; copper; integrated circuit interconnections; CMOS transistors; CMP planarization; Cu; Cu interconnects; RC delay reduction; ULSI scaling; VLSI interconnect process integration; capacitance; gate electrodes; low-k interlayer dielectrics; parasitic resistance reduction; resistivity; salicide technologies; source/drain electrodes; sub-quarter micron CMOSFETs; CMOS technology; Conductivity; Copper; Delay; Dielectric materials; Electrodes; Parasitic capacitance; Planarization; Ultra large scale integration; Very large scale integration;
Conference_Titel :
Solid-State and Integrated Circuit Technology, 1998. Proceedings. 1998 5th International Conference on
Conference_Location :
Beijing
Print_ISBN :
0-7803-4306-9
DOI :
10.1109/ICSICT.1998.785781
