Abstract :
A 0.25 μm CMOS technology, with 6 layers of fully planarized interconnect, has been developed for versatile, flexible, and fast turn-around foundry manufacturing. A 0.6 μm layout pitch has been successfully demonstrated for active, gate poly, and first metal layers. The 0.25 μm, 50 A Tox and the 0.35 μm, 65 A Tox devices were designed to support the 2.5 V core and the 3.3 V I/O circuits respectively on the same chip. In addition, high-performance 0.8 μm, 40 A Tox transistors are also available for low-power applications at 1.8 V Vcc. Gate-delay is 40-35 ps at 2.5 V for the 0.25 μm device, and sub-30 ps at 1.8 V for the 0.18 μm device. The embedded 6T SRAM cell size is 6.34 μm2. Considerations in process architecture and device design, relevant to foundry manufacturing, are also addressed on this 6-level-metal 0.25 μm CMOS technology
Keywords :
CMOS integrated circuits; ULSI; integrated circuit manufacture; integrated circuit metallisation; integrated memory circuits; low-power electronics; 0.18 to 0.25 micron; 0.6 micron; 1.8 to 3.3 V; 6-level-metal CMOS process; DRAM; deep submicron technology; embedded 6T SRAM cell size; foundry manufacturing; fully planarized interconnect; low-power applications; process architecture; CMOS process; CMOS technology; Dielectrics; Flexible manufacturing systems; Foundries; Integrated circuit interconnections; Manufacturing processes; Planarization; Random access memory; Semiconductor device manufacture;
