DocumentCode :
3063051
Title :
A comparison of two SAR processing architectures for VLSI implementation
Author :
Friedlander, Benjamin ; Newkirk, John
Author_Institution :
Stanford University, Stanford, CA
Volume :
8
fYear :
1983
fDate :
30407
Firstpage :
919
Lastpage :
922
Abstract :
Digital processing of Synthetic Aperture Radar (SAR) data requires very large amounts of computation. In this paper we consider the feasibility of a VLSI implementation of the azimuth compression part of a real-time SAR processor. The area/size requirements of such a processor are evaluated by means of a prototype design. Two processing architectures are compared in terms of their suitability for VLSI implementation.
Keywords :
Azimuth; Computer architecture; Concurrent computing; Correlators; Distributed computing; Prototypes; Radar imaging; Spaceborne radar; Synthetic aperture radar; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Acoustics, Speech, and Signal Processing, IEEE International Conference on ICASSP '83.
Type :
conf
DOI :
10.1109/ICASSP.1983.1172027
Filename :
1172027
Link To Document :
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