Title :
A high-performance and energy-efficient FFT implementation on super parallel processor (MX) for mobile multimedia applications
Author :
Sugimura, Takeaki ; Yamasaki, Hiroyuki ; Noda, Hideyuki ; Yamamoto, Osamu ; Okuno, Yoshihiro ; Arimoto, Kazutami
Author_Institution :
Syst. Core Technol. Div., Renesas Technoloty Corp., Itami
Abstract :
A super parallel embedded processor core (MX core) for SoC (System on Chip) has been developed for multi-media application such as real-time signal processing and image processing. The developed processor realizes high processing performance, small area, low power operation and flexible programmability simultaneously. This paper describes an implementation of high-performance and energy-efficient FFT operation on the MX core for mobile multimedia application. As the result of the implementation, MX core realizes 137 to 211 times faster than 32 bit general purpose RISC processor. In addition, energy dissipation is 23.9 to 36.7 times more efficient. This high performance and energy efficient parallel processing operation enhances the real time signal processing usage for embedded systems.
Keywords :
microprocessor chips; mobile communication; multimedia communication; system-on-chip; FFT implementation; MX core; RISC processor; embedded processor core; image processing; mobile multimedia applications; parallel processor; real-time signal processing; system-on-chip; Embedded system; Energy dissipation; Energy efficiency; Image processing; Multimedia systems; Parallel processing; Real time systems; Reduced instruction set computing; Signal processing; System-on-a-chip; SIMD; low power; parallel FFT; parallel processor; signal and image processing;
Conference_Titel :
Intelligent Signal Processing and Communications Systems, 2008. ISPACS 2008. International Symposium on
Conference_Location :
Bangkok
Print_ISBN :
978-1-4244-2564-8
Electronic_ISBN :
978-1-4244-2565-5
DOI :
10.1109/ISPACS.2009.4806746
