DocumentCode
3063162
Title
VLSI architecture for a decoder for Hermitian codes
Author
O´Sullivan, Michael E. ; Pope, Stphen P.
Author_Institution
Dept. of Math., Puerto Rico Univ., Mayaguez, Puerto Rico
fYear
1997
fDate
29 Jun-4 Jul 1997
Firstpage
376
Abstract
Algebraic geometry (AG) codes have long been recognized as theoretically powerful nonbinary block codes which equal or exceed the power of Reed-Solomon codes. However, there is a question of whether implementation of AG decoders is too complex to be practical. In this paper, we present algorithmic and architectural results that demonstrate how powerful AG decoders can be built with reasonable complexity-on the same order of complexity as that commonly devoted to Reed-Solomon decoding, and well within the capabilities of modern CMOS integrated-circuit technology
Keywords
CMOS integrated circuits; VLSI; algebraic geometric codes; block codes; decoding; CMOS integrated-circuit technology; Hermitian codes; VLSI architecture; agebraic geometry codes; algorithm; decoder; error locators; gate counts; nonbinary block codes; Block codes; CMOS technology; Decoding; Error correction codes; Geometry; Mathematics; Polynomials; Reed-Solomon codes; Testing; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Information Theory. 1997. Proceedings., 1997 IEEE International Symposium on
Conference_Location
Ulm
Print_ISBN
0-7803-3956-8
Type
conf
DOI
10.1109/ISIT.1997.613313
Filename
613313
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