Computationally efficient implementation of sparse-tap FIR adaptive filters with tap-position control on Intel IA-32 processors

This paper presents an computationally efficient implementation of sparse-tap FIR adaptive filters with tap-position control on Intel IA-32 processors with single-instruction multiple-data (SIMD) capability. In order to overcome random-order memory access which prevents a vectorization, a block-based processing and a re-ordering buffer are introduced. A dynamic register allocation and the use of memory-to-register operations help the maximization of the loop-unrolling level. Up to 66 percent speedup is achieved.