A methodology for implementing pipelined fixed-point infinite impulse response filters

This paper outlines a methodology for implementing pipelined IIR digital filters that considers both how much pipelining to use and what fixed-point precisions are required. The methodology is applied to an example second-order IIR filter implemented on a field programmable gate array; the results show that the methodology allows exploration of the trade-offs between hardware size and throughput while ensuring that the implemented filters deliver a consistent quality of output.