A real-time VLSI-based architecture for multi-motion estimation

Author

Legat, J.-D. ; Cornil, J.P. ; Macq, D. ; Verleysen, M.

Author_Institution

Microelectronics Lab., Univ. Catholique de Louvain, Louvain-La-Neuve, Belgium

fYear

1992

fDate

30 Aug-3 Sep 1992

Firstpage

147

Lastpage

150

Abstract

This paper describes a new parallel architecture dedicated to multi-motion estimation. The input image is scanned by a standard video camera with 256 grey levels. Motion computing is based on the optical flow determination. Some constraints are proposed to allow multi-motion evaluation. The algorithm is presented and the main features of a 1-D systolic architecture which is based on a custom VLSI chip is given. This architecture allows a real-time implementation of the multi-motion estimation algorithm

Keywords

VLSI; digital signal processing chips; image processing equipment; motion estimation; parallel architectures; real-time systems; systolic arrays; 1-D systolic architecture; 256 grey levels; custom VLSI chip; multi-motion estimation; optical flow determination; parallel architecture; real-time VLSI-based architecture; Brightness; Cameras; Computer architecture; Differential equations; Image motion analysis; Image sequences; Laboratories; Motion estimation; Optical computing; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Pattern Recognition, 1992. Vol. IV. Conference D: Architectures for Vision and Pattern Recognition, Proceedings., 11th IAPR International Conference on

Conference_Location

The Hague

Print_ISBN

0-8186-2925-8

Type

conf

DOI

10.1109/ICPR.1992.202152

Filename

202152