Discussion on the low-power CMOS latches and flip-flops

Author

Xiaohai, Qiu ; Hongyi, Chen

Author_Institution

Inst. of Microelectron., Tsinghua Univ., Beijing, China

fYear

1998

fDate

23-23 Oct. 1998

Firstpage

477

Lastpage

480

Abstract

Latches and flip-flops used in low power circuits are discussed in this paper. Two kinds of latches of 5-T and 4-T are evolved from the standard 8-T static latch for low power application. Simulation results show that the 4-T latch has the lowest power consumption with no speed penalty. The 4-T latch is usually considered as dynamic. However, detailed analysis shows that it may be static under certain conditions, which are also given in this paper. Single-edge-trigged (SET) flip-flops and double-edge-trigged (DET) flip-flop based on these latches are also presented. Significant power and area savings can achieve by using 4-T latches.

Keywords

CMOS logic circuits; flip-flops; low-power electronics; 4-T latches; 5-T latches; double-edge-trigged type; dynamic latch; low power circuits; low-power CMOS flip-flops; low-power CMOS latches; single-edge-trigged type; static latch; Circuit simulation; Clocks; Energy consumption; Flip-flops; Latches; MOS devices; Microelectronics; Positron emission tomography; Threshold voltage; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State and Integrated Circuit Technology, 1998. Proceedings. 1998 5th International Conference on

Conference_Location

Beijing, China

Print_ISBN

0-7803-4306-9

Type

conf

DOI

10.1109/ICSICT.1998.785925

Filename

785925