Title :
An optimization design of CMOS buffer using RSM technique
Author :
Gan, Xuewen ; Zhu, Hailun
Author_Institution :
Inst. of Microelectron., Beijing Univ., China
Abstract :
This paper presents an optimization design method for a CMOS buffer. A model equation for CMOS buffer delay time has been derived using the RSM experiment design technique. An optimization was then performed by means of the equations of the delay time and silicon area to obtain the optimum number of stages and the size scale factor for the CMOS buffer, which meets the requirement of delay time while having the minimum area, or achieving the minimum delay time with acceptable area. The optimization design method and the related software can also be used for other problems
Keywords :
CMOS logic circuits; buffer circuits; circuit CAD; circuit optimisation; delay estimation; integrated circuit design; logic CAD; surface fitting; CMOS buffer; RSM technique; Si area; buffer delay time; delay time modelling; model equation; optimization design; size scale factor; CMOS logic circuits; Capacitance; Delay effects; Design methodology; Design optimization; Equations; Inverters; MOSFET circuits; Semiconductor device modeling; Silicon;
Conference_Titel :
Solid-State and Integrated Circuit Technology, 1998. Proceedings. 1998 5th International Conference on
Conference_Location :
Beijing
Print_ISBN :
0-7803-4306-9
DOI :
10.1109/ICSICT.1998.785926
