A new approach on power estimation of CMOS sequential logic circuits

Author

Zhu, Ning ; Zhou, Run-De ; Yang, Xing-Zi

Author_Institution

Inst. of Microelectron., Tsinghua Univ., Beijing, China

fYear

1998

fDate

1998

Firstpage

488

Lastpage

491

Abstract

Power estimation for CMOS sequential circuits is difficult because of sequential feedback loops embedded in the circuits. This paper presents a new method which applies probabilistic propagation and an iteration method to obtain the transition probability of circuit internal nodes. The time and space complexity of computation is improved by compacting the circuit before calculation. Experimental results show that our method is applicable even for large sequential circuits

Keywords

CMOS logic circuits; circuit analysis computing; computational complexity; estimation theory; iterative methods; probability; sequential circuits; CMOS sequential logic circuits; circuit compaction; circuit internal nodes; iteration method; large sequential circuits; power estimation; probabilistic propagation; sequential feedback loops; space complexity; time complexity; transition probability; Cams; Circuit simulation; Computational modeling; Feedback circuits; Feedback loop; Logic circuits; Microelectronics; Probability; Registers; Sequential circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State and Integrated Circuit Technology, 1998. Proceedings. 1998 5th International Conference on

Conference_Location

Beijing

Print_ISBN

0-7803-4306-9

Type

conf

DOI

10.1109/ICSICT.1998.785928

Filename

785928