A high speed multiplication-and-accumulation design methodology for submicron and deep submicron DSP solutions

Author

Zhu Yajlang ; Lingyi, Huang ; Yulin, Qiu ; Xia, Chen ; Xiaoling, Huang

Author_Institution

Microelectron. R&D Center, Acad. Sinica, Beijing, China

fYear

1998

fDate

1998

Firstpage

502

Lastpage

504

Abstract

Due to the rapid expansion of the application areas of digital signal processing (DSP), various fast multiplication-and-accumulation (MAC) modules are required by system developers. In this paper, a high speed and random logic structure MAC design methodology is presented with Wallace trees and borrow-select subtracters (BSSs) as the architecture of the MAC. EDA tools can be utilized to perform automatic placement and routing. A 16*12 MAC and a complex 16*12 MAC with both real and imagine parts are designed by applying this methodology for a 1-million-transistor DSP chip. Simulation results of the modules in 0.6 μm CMOS technology are encouraging

Keywords

CMOS digital integrated circuits; circuit CAD; circuit layout CAD; digital arithmetic; digital signal processing chips; high level synthesis; high-speed integrated circuits; integrated circuit design; multiplying circuits; network routing; 0.6 micron; CMOS technology; EDA tool; MAC modules; Wallace trees; automatic placement; automatic routing; borrow-select subtracters; deep submicron DSP chips; design methodology; digital signal processing; high speed multiplication/accumulation; random logic structure; submicron DSP chips; Automatic logic units; Bismuth; CMOS technology; Delay; Design methodology; Electronic design automation and methodology; Logic design; Signal processing; Signal processing algorithms; Wiring;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State and Integrated Circuit Technology, 1998. Proceedings. 1998 5th International Conference on

Conference_Location

Beijing

Print_ISBN

0-7803-4306-9

Type

conf

DOI

10.1109/ICSICT.1998.785931

Filename

785931