Title :
A VLSI architecture for hierarchical scene matching
Author :
Venkatesan, Raguveer ; Sastry, Raghu ; Ranganathan, N.
Author_Institution :
Center for Microelectronics Res., Univ. of South Florida, Tampa, FL, USA
fDate :
30 Aug-3 Sep 1992
Abstract :
Scene matching is the problem of matching regions of two images of the same scene taken by different sensors at different times or under different viewing conditions. Hierarchical scene matching generates a multiresolution pyramid of the images to be matched. The authors describe hierarchical scene matching technique, related work and their proposed VLSI architecture. They present a description of the three subsystems-pyramid generation block, exhaustive search block and template match block. Then they briefly describe the performance attainable with the proposed architecture which uses a large amount of parallelism and pipelining
Keywords :
VLSI; image processing equipment; image recognition; parallel architectures; pattern recognition equipment; pipeline processing; VLSI architecture; exhaustive search block; hierarchical scene matching; multiresolution pyramid; parallelism; pipelining; pyramid generation block; region matching; template match block; viewing conditions; Computer architecture; Computer science; Hardware; Image resolution; Layout; Microelectronics; Pipeline processing; Software algorithms; Testing; Very large scale integration;
Conference_Titel :
Pattern Recognition, 1992. Vol. IV. Conference D: Architectures for Vision and Pattern Recognition, Proceedings., 11th IAPR International Conference on
Conference_Location :
The Hague
Print_ISBN :
0-8186-2925-8
DOI :
10.1109/ICPR.1992.202169