Title :
A high speed base library and macro library design methodology for submicron and deep submicron ULSI
Author :
Lingyi, Huang ; Zhu Uajiang ; Yuling, Qiu ; Qing, Ye ; Chaoshu, Chen ; Xiaodong, Chen ; Zhenjiang, Su ; Zhao, Liu ; YuHui, Wang ; Xia, Chen
Author_Institution :
Microelectron. R&D Center, Acad. Sinica, Beijing, China
Abstract :
This paper presents a high speed base library and macro library design methodology for submicron and deep submicron ULSI. Using the libraries, a 0.6 μm CMOS high speed DSP chip is developed. To create the base and macro libraries, the effects of delay in interconnect wire and input slope were considered; the delay model was selected, the “variable parameter” cell and “buried” cell were used to correct a timing violation
Keywords :
CMOS digital integrated circuits; ULSI; application specific integrated circuits; circuit CAD; circuit layout CAD; delay estimation; digital signal processing chips; high level synthesis; high-speed integrated circuits; integrated circuit design; timing; 0.6 micron; ASIC design; CMOS high speed DSP chip; buried cell; deep submicron ULSI; delay model; design methodology; high speed base library; high speed macro library; input slope; interconnect wire delays; submicron ULSI; timing violation correction; variable parameter cell; Capacitance; Delay effects; Design methodology; Digital signal processing chips; Flowcharts; Integrated circuit interconnections; Libraries; Timing; Ultra large scale integration; Wire;
Conference_Titel :
Solid-State and Integrated Circuit Technology, 1998. Proceedings. 1998 5th International Conference on
Conference_Location :
Beijing
Print_ISBN :
0-7803-4306-9
DOI :
10.1109/ICSICT.1998.785932
