DocumentCode
3064994
Title
A new design methodology using simulation for on-chip ESD protection designs for integrated circuits
Author
Wang, Albert Z. ; Tsay, Chen H.
Author_Institution
Nat. Semicond. Corp., Santa Clara, CA, USA
fYear
1998
fDate
1998
Firstpage
509
Lastpage
512
Abstract
A new design methodology was developed for IC on-chip ESD protection design using a full-scale, mixed-mode simulation approach. The complete design procedure and design examples are discussed and reasonably good design prediction was observed in using this novel design methodology
Keywords
circuit CAD; circuit simulation; electrostatic discharge; integrated circuit design; protection; IC onchip protection design; design methodology; integrated circuits; mixed-mode simulation; on-chip ESD protection; Biological system modeling; Breakdown voltage; Circuit simulation; Costs; Coupling circuits; Design methodology; Discrete event simulation; Electrostatic discharge; Medical simulation; Protection;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State and Integrated Circuit Technology, 1998. Proceedings. 1998 5th International Conference on
Conference_Location
Beijing
Print_ISBN
0-7803-4306-9
Type
conf
DOI
10.1109/ICSICT.1998.785933
Filename
785933
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