DocumentCode
3065043
Title
A low-cost architecture for real-time processing and analysis of binary images
Author
Hugen, F.M. ; Bulsink, B.
Author_Institution
Control Syst. & Comput. Eng., Lab., Fac. of Electr. Eng., Twente Univ., Enschede, Netherlands
fYear
1992
fDate
30 Aug-3 Sep 1992
Firstpage
229
Lastpage
232
Abstract
An architecture is presented for low-cost and flexible realisation of image processing and analysis algorithms of binary images. The flexibility of the architecture is due to reconfigurable network of simple boolean functions. It is shown that this architecture can readily be implemented by low-cost off-the-shelf components. This is illustrated by some simulations of a hypothetical realisation
Keywords
image processing; image processing equipment; parallel architectures; real-time systems; reconfigurable architectures; binary images; boolean functions; image analysis architecture; real-time processing; reconfigurable network; Algorithm design and analysis; Application software; Computer architecture; Hardware; Image analysis; Image processing; Image segmentation; Labeling; Reconfigurable architectures; Silicon;
fLanguage
English
Publisher
ieee
Conference_Titel
Pattern Recognition, 1992. Vol. IV. Conference D: Architectures for Vision and Pattern Recognition, Proceedings., 11th IAPR International Conference on
Conference_Location
The Hague
Print_ISBN
0-8186-2925-8
Type
conf
DOI
10.1109/ICPR.1992.202173
Filename
202173
Link To Document