Channel formation for 0.15 μm CMOS using through-the-gate implantation

Front-end optimization of a 0.15 μm CMOS technology is described demonstrating the feasibility of a Through-the-Gate implantation (TGi) concept for super-steep retrograde well formation. In this paper we show for the first time that excellent transistor matching of NMOS devices with TGi processing is obtained. It demonstrates the absence of any anomalies due to stochastic effects associated with this novel approach for boron super-steep retrograde well formation and excellent 0.15 μm CMOS transistor and circuit performance was obtained