A CMOS parallel Gouraud shading VLSI architecture

The authors examine the various hardware methodologies used to accelerate image rendering. An architecture capable of being implemented on a VLSI chip to effectively carry out this objective is presented. The architecture uses inherent parallelism in the rendering algorithm and processes multiple scan lines simultaneously. The architecture is scalable with multiple copies of the chip and a set up processor being used to enhance output. Use of memory interlacing and banks avoids the possibility of memory bandwidth posing a bottleneck. The Gouraud shading algorithm was chosen for implementation. The simulation of the architecture is discussed