DocumentCode
3066262
Title
A case for a multitrace cluster
Author
Wu, Yiu Cheong Simon ; Ling, John ; Helms, Ward J.
Author_Institution
Dept. of Electr. Eng., Washington Univ., Seattle, WA, USA
fYear
1999
fDate
1999
Firstpage
42
Lastpage
45
Abstract
The ability to place vast transistor count on a single chip offers designers to experiment with a new architecture. A new architecture alternatives, known as Mulitrace Cluster, is proposed to overcome the limits of circuit technology and microarchitecture
Keywords
computer architecture; microprocessor chips; multitrace cluster architecture; single chip; superscalar processor; Computer aided software engineering; Decoding; Delay; Dynamic scheduling; Hardware; Integrated circuit technology; Microarchitecture; Microprocessors; Technological innovation; Transistors;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Technology, Systems, and Applications, 1999. International Symposium on
Conference_Location
Taipei
ISSN
1524-766X
Print_ISBN
0-7803-5620-9
Type
conf
DOI
10.1109/VTSA.1999.785995
Filename
785995
Link To Document