Title :
Exploiting bit-level parallelism in Boolean matrix operations for graph analysis
Author :
Jackson, David Jeff ; Whiteside, Dennis M. ; Wurtz, L.T.
Author_Institution :
Dept. of Electr. Eng., Alabama Univ., Tuscaloosa, AL, USA
Abstract :
A number of important characteristics for a graph, which may represent a set of parallel application tasks or a parallel computer architecture, can be extracted by analyzing the Boolean matrix corresponding to the graph. The characteristic of concern is the determination of minimum path lengths for various classes of regularly structured graphs. All the example graphs vary in terms of connectivity and sparsity and provide a suitable testbed for the analysis of the various algorithms used in determining powers of the Boolean matrices. Improvements for these algorithms are introduced which exploit the Boolean nature of the matrices and the inherent bit-level parallelism available in any N-bit computer system. An algorithm is introduced which exploits this bit-level parallelism and a number of graphs were analyzed utilizing a high-performance IBM RS/6000 workstation to demonstrate the merits of the algorithm
Keywords :
Boolean algebra; graph theory; parallel algorithms; Boolean matrices; Boolean matrix operations; IBM RS/6000 workstation; bit-level parallelism; connectivity; graph analysis; minimum path lengths; parallel application tasks; parallel computer architecture; sparsity; Algorithm design and analysis; Application software; Binary trees; Computer architecture; Concurrent computing; Hypercubes; Parallel processing; Performance analysis; Sparse matrices; Workstations;
Conference_Titel :
Southeastcon '92, Proceedings., IEEE
Conference_Location :
Birmingham, AL
Print_ISBN :
0-7803-0494-2
DOI :
10.1109/SECON.1992.202252