A high-speed built-in-self-test design for DRAMs

Author

Huang, Shi-Yu ; Kwai, Ding-Ming

Author_Institution

Design Service & Product Eng. Center, Worldwide Semicond. Manuf Corp., Hsinchu, Taiwan

fYear

1999

fDate

1999

Firstpage

50

Lastpage

53

Abstract

A high-speed Built-In Self-Test (BIST) design for Dynamic Random Access Memories (DRAMs) is proposed. The circuit automatically generates a sequence of pre-defined test patterns for on-chip DRAM testing. The innovation herein is mainly an architecture consisting of two finite state machines, instead of the conventional single finite state machine. Based upon this novel architecture, the pipeline technique can then be applied to divide the pattern generation process into stages, leading to a higher-speed design. In addition to pipelining, a technique referred to as protocol-based relaxation is also incorporated. This technique, imposing a certain protocol on the two communicating finite state machines, further relaxes the timing criticality of the design. Synthesis results show that the proposed BIST circuit can operate at the speed of as high as 400 MHz using 0.35 um CMOS technology

Keywords

CMOS memory circuits; DRAM chips; built-in self test; finite state machines; high-speed integrated circuits; integrated circuit design; integrated circuit testing; pipeline processing; 0.35 micron; 400 MHz; CMOS technology; DRAM; built-in self-test; finite state machine; high-speed design; on-chip testing; pipeline technique; relaxation protocol; Automata; Automatic test pattern generation; Automatic testing; Built-in self-test; CMOS technology; Circuit testing; DRAM chips; Pipeline processing; Random access memory; Test pattern generators;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, Systems, and Applications, 1999. International Symposium on

Conference_Location

Taipei

ISSN

1524-766X

Print_ISBN

0-7803-5620-9

Type

conf

DOI

10.1109/VTSA.1999.785997

Filename

785997