Title :
An efficient architecture for two-dimensional discrete wavelet transform
Author :
Wu, Po-Cheng ; Chen, Liang-Gee
Author_Institution :
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Abstract :
This paper proposes an efficient architecture for the two-dimensional discrete wavelet transform (2-D DWT). The proposed architecture includes a transform module, a RAM module, and a multiplexer. In the transform-module, we employ the polyphase decomposition technique to the decimation filters of stage 1, and the coefficient folding technique to the decimation filters of stage 2. The RAM size is N/2×N/2. In comparison with other 2-D DWT architectures, the advantages of the proposed architecture are the near 100% hardware utilization, fast computation time, regular data flow, and low complexity control circuit, making this architecture suitable for next generation image compression systems
Keywords :
digital signal processing chips; discrete wavelet transforms; RAM module; VLSI architecture; coefficient folding; decimation filter; image compression; multiplexer; polyphase decomposition; transform module; two-dimensional discrete wavelet transform; Circuits; Computer architecture; Control systems; Data flow computing; Discrete transforms; Discrete wavelet transforms; Filters; Hardware; Multiplexing; Two dimensional displays;
Conference_Titel :
VLSI Technology, Systems, and Applications, 1999. International Symposium on
Conference_Location :
Taipei
Print_ISBN :
0-7803-5620-9
DOI :
10.1109/VTSA.1999.786013