• DocumentCode
    3066651
  • Title

    A high efficient multiplier for the RS decoder

  • Author

    Jeng, J.H. ; Kuo, J.M. ; Tnuong, T.K.

  • Author_Institution
    Dept. of Electr. Eng., I-Shou Univ., Taiwan
  • fYear
    1999
  • fDate
    1999
  • Firstpage
    116
  • Lastpage
    118
  • Abstract
    The field element multiplication plays an important role in the VLSI implementation of an RS decoder. In this paper, a high efficient multiplier is derived, which removes all the redundant computations. The fast multiplier uses only 64 AND gates and 83 XOR gates, and the total gate delay is 6
  • Keywords
    Reed-Solomon codes; VLSI; decoding; digital signal processing chips; multiplying circuits; AND gate; RS decoder; VLSI architecture; XOR gate; multiplier; Clocks; Concurrent computing; DVD; Decoding; Delay effects; Error correction codes; Matrix converters; Polynomials; Reed-Solomon codes; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Technology, Systems, and Applications, 1999. International Symposium on
  • Conference_Location
    Taipei
  • ISSN
    1524-766X
  • Print_ISBN
    0-7803-5620-9
  • Type

    conf

  • DOI
    10.1109/VTSA.1999.786014
  • Filename
    786014
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3066651