A general second-order lock detector for type I PLLs

A simple phase-locked-loop (PLL) lock detector can be constructed from a quadrature phase detector. Unfortunately, a DC component may exist in this detector´s output under false lock conditions. This DC component may operate a phase-locked receiver´s coherent automatic gain control (AGC) system. It is possible that the AGC system could adjust the receiver gain to produce a nominal value for the unwanted DC component. The receiver would appear to be operating properly when, in fact, it was not. A PLL lock theory is presented, and an ideal detector is discussed which is free of this problem. The first-order approximation of the ideal lock detector is shown to be the classical phase quadrature lock detector. This is followed by the development of a second-order approximation of the ideal detector. Finally, the theory is applied to a simple example, and a block diagram of a second-order lock detector for this example is given