A Cost-Effective Noise-Reduction Filtering Structure Based on Unsymmetrical Working Windows

In this paper, we propose a fast, efficient algorithm and the associated VLSI architecture to perform the impulse-noise reduction for image pixels. The algorithm proposed here is developed with the principle that the horizontal and vertical, nearly neighboring pixels are more significantly correlated to a pixel than other distant ones. We conduct a few first- level simulations of our algorithm to prove its effectiveness. Then the associated VLSI architecture is coded with Verilog-HDL and the codes are simulated and verified in Quartus-II environment. The architecture is implemented in a FPGA, and the FPGA serves on a real-time platform to demonstrate the performance of our algorithm.