Multiplier-less design of FIR filters

In many real time applications such as in communications, digital filters are to be implemented in hardware. In a hardware realization, to reduce cost, it is highly desirable to minimize the number of general multiplications. Whereas multiplications by fixed powers of two are very easy to implement in hardware. In this paper, a new technique to design FIR filters is presented. The filters designed by this technique require only additions and powers of two multiplications for their implementation. They do not require any general multiplications. This technique has been successfully used to design DTMF/MF receivers in telephony which require only a few additions. Low-pass and band-pass filters with excellent stop-band attenuation and very flat pass-band response have also been designed. The filters designed by this technique are particularly well suited for custom VLSI implementation.