Title :
Design and simulation of addressable failure site test structure for IC process control monitor
Author :
Doong, Kelvin Yih-Yuh ; Cheng, Jye-Yen ; Hsu, Charles Ching-Hsiang
Author_Institution :
Worldwide Semicond. Manuf. Corp., Shinchu, Taiwan
Abstract :
A novel test structure to ensure failure addressable and high-density test structure of semiconductor process control monitor with a limited number of contact pads required for electrical test is described. The placement and routing scheme requires only two levels of conductive layers, and provides the maximum number of bridging and continuity test structure units. A graph model is developed to manifest the spatial configuration of test structure units and simplify the complexity of fault detection. Also, a generic algorithm of multi-fault detection was developed.
Keywords :
failure analysis; fault diagnosis; integrated circuit manufacture; probes; process monitoring; production testing; IC process control monitor; addressable failure site test structure; bridging structure units; conductive layers; contact pads; continuity test structure units; electrical test; fault detection; generic algorithm; high-density test structure; multi-fault detection; semiconductor process control monitor; spatial configuration; Application specific integrated circuits; Circuit testing; Condition monitoring; Contacts; Geometry; Integrated circuit testing; Probes; Process control; Semiconductor device testing; Semiconductor process modeling;
Conference_Titel :
VLSI Technology, Systems, and Applications, 1999. International Symposium on
Print_ISBN :
0-7803-5620-9
DOI :
10.1109/VTSA.1999.786039
