Broadband digital correlator design using Vertex-2 FPGAs

Author

Lin, Zhenhui ; Zuo, Yingxi ; Yao, Qijun

Author_Institution

Purple Mountain Obs., Acad. Sinica, Nanjing, China

fYear

2004

fDate

24-27 Aug. 2004

Firstpage

375

Lastpage

377

Abstract

This paper presents a design of a 2-bit, 4-level digital correlator implemented with Xilinx Vertex-2 FPGAs. A technique of serial-to-parallel conversion of die input streams is adopted to reduce the speed requirement of the correlation circuits. The correlator can be used for auto- and cross-correlation, and is fully cascadable to form more lags with more FPGA chips. It can run at a clock of 250 MHz. and thus can manipulate input signals with bandwidth of 500 MHz thanks to the 1:4 serial-to-parallel converting scheme.

Keywords

correlators; field programmable gate arrays; integrated circuit design; logic design; parallel processing; 2 bit; 250 MHz; 500 MHz; Xilinx Vertex-2 FPGA; auto-correlation; broadband digital correlator design; cascadable correlator; correlation circuit speed requirement; correlator clock; cross-correlation; input bandwidth; input streams; lags; serial-to-parallel conversion; serial-to-parallel converting scheme; Bandwidth; Circuits; Clocks; Correlators; Field programmable gate arrays; Frequency; Signal processing; Signal sampling; Telescopes; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Radio Science Conference, 2004. Proceedings. 2004 Asia-Pacific

Print_ISBN

0-7803-8404-0

Type

conf

DOI

10.1109/APRASC.2004.1422488

Filename

1422488