Title :
2.5 Ω/□ W/TiN/poly stack gate technology for high density and embedded DRAM technology
Author :
Hu, Yin ; Anderson, Dirk ; Rotondaro, Antonio ; Obrien, Sean ; Hsu, Wei-Yung ; Kraft, Robert ; Tiner, Paul ; Nicollian, Paul ; Aur, Shiann
Author_Institution :
Silicon Technol. Dev. Center, Texas Instrum. Inc., Dallas, TX, USA
Abstract :
A W/TiN/Poly gate stack has been developed and extensively characterized, and it is applied to a 0.2 μm CMOS transistor design for Gigabit and embedded DRAM technology. The gate sheet is less than 2.5 Ω/□ with a 600 Å/200 Å/900 Å W/TiN/Poly gate stack at 0.16 μm line width. The effective oxide thickness is found to be 3 Å thicker than a comparable poly-only gate. The oxide hard breakdown field can exceed 12 MV/cm and CHC lifetime is greater than 10 years with the W/TiN/Poly gate stack technology. In addition, a drive current of 400 μA/μm for nMOS and 190 μA/μm for pMOS have been achieved at 1 pA/μm off-current and 1.8 V Vcc with 5 nm gate oxide. This is the highest drive current reported to date for similar technologies
Keywords :
CMOS memory circuits; DRAM chips; embedded systems; integrated circuit interconnections; integrated circuit reliability; semiconductor device breakdown; titanium compounds; tungsten; 0.16 mum; 0.2 mum; 1.8 V; 10 year; 200 to 900 angstrom; 5 nm; CHC lifetime; CMOS transistor design; Si-SiO2; W-TiN-Si; W/TiN/poly stack gate technology; drive current; effective oxide thickness; embedded DRAM technology; gate oxide integrity; gate oxide reliability; gate sheet; high density; line width; oxide hard breakdown field; CMOS technology; Doping; Energy consumption; Hot carriers; Implants; Logic circuits; MOS devices; Random access memory; Threshold voltage; Tin;
Conference_Titel :
VLSI Technology, Systems, and Applications, 1999. International Symposium on
Conference_Location :
Taipei
Print_ISBN :
0-7803-5620-9
DOI :
10.1109/VTSA.1999.786046
