DocumentCode
3067302
Title
LDPC codes for rank modulation in flash memories
Author
Zhang, Fan ; Pfister, Henry D. ; Jiang, Anxiao
Author_Institution
Electr. & Comput. Eng. Dept., Texas A&M Univ., College Station, TX, USA
fYear
2010
fDate
13-18 June 2010
Firstpage
859
Lastpage
863
Abstract
An LDPC code is proposed for flash memories based on rank modulation. In contrast to previous approaches, this enables the use of long ECCs with fixed-length modulation codes. For ECC design, the rank modulation scheme is treated as part of an equivalent channel. A probabilistic model of the equivalent channel is derived and a simple high-SNR approximation is given. LDPC codes over integer rings and finite fields are designed for the approximate channel and a low-complexity symbol-flipping verification-based (SFVB) message-passing decoding algorithm is proposed to take advantage of the channel structure. Density evolution (DE) is used to calculate decoding thresholds and simulations are used to compare the low-complexity decoder with sum-product decoding.
Keywords
approximation theory; channel coding; computational complexity; decoding; flash memories; modulation coding; parity check codes; probability; ECC design; LDPC codes; channel structure; density evolution; equivalent channel; finite fields; flash memories; high-SNR approximation; low-complexity decoder; probabilistic model; rank modulation; sum-product decoding; symbol-flipping verification-based message-passing decoding; Algorithm design and analysis; Computer science; Decoding; Error correction codes; Flash memory; Galois fields; Modulation coding; Nonvolatile memory; Parity check codes; Tunneling;
fLanguage
English
Publisher
ieee
Conference_Titel
Information Theory Proceedings (ISIT), 2010 IEEE International Symposium on
Conference_Location
Austin, TX
Print_ISBN
978-1-4244-7890-3
Electronic_ISBN
978-1-4244-7891-0
Type
conf
DOI
10.1109/ISIT.2010.5513603
Filename
5513603
Link To Document