AES-128 Implementation on a Virtex-4 FPGA

A VHDL (very high-speed integrated circuit hardware description language) implementation of 128-bit AES (advanced encryption standard) on a Xilinx XC4VFX12 Virtex-4 Pro FPGA (field-programmable gate array) and ML403 board is developed from a Verilog design that adheres to FIPS-197 (federal information processing standard 197). The following features are added: automatic start of transform, CBC (cipher-block chaining) mode, key permutation value readout, transfer and store, and output of each intermediate state value. The core processing rate achieves 582 to 640 Mbps; 30 Mbps is achieved in practice, via peripheral register access. A demonstration GUI (graphical user interface), written in Microsoft visual C++ version 6.0, running on a PC, interfaces to the ML403 board via RS232.